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8-Bit, 250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9284
FEATURES
Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 250 MSPS SFDR: 65 dBc at 200 MHz input at 250 MSPS Low power: 314 mW at 250 MSPS On-chip reference and track-and-hold 1.2 V p-p analog input range for each channel Differential input with 500 MHz bandwidth LVDS-compliant digital output DNL: 0.2 LSB Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Built-in selectable digital test pattern generation Pin-programmable power-down function Available in 48-lead LFCSP
GENERAL DESCRIPTION
The AD9284 is a dual 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports simultaneous operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 250 MSPS conversion rate with outstanding dynamic performance. The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible. The AD9284 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of -40C to +85C.
PRODUCT HIGHLIGHTS
1. 2. 3. Integrated Dual 8-Bit, 250 MSPS ADC. Single 1.8 V Supply Operation with LVDS Outputs. Power-Down Option Controlled via a Pin-Programmable Setting.
APPLICATIONS
Communications Diversity radio systems I/Q demodulation systems Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber
FUNCTIONAL BLOCK DIAGRAM
SDIO/ PWDN CSB SCLK OE
CLK- VIN+A VIN-A VCM VREF 1.0V VREF REF SELECT x1.5 CLOCK MANAGEMENT ADC
LVDS OUTPUT BUFFER
CLK+
SPI
D7+ (MSB), D7- (MSB) D0+ (LSB), D0- (LSB) (CHANNEL A)
DCO GENERATION
DCO+ DCO-
VIN-B VIN+B ADC
LVDS OUTPUT BUFFER
D7+ (MSB), D7- (MSB) D0+ (LSB), D0- (LSB) (CHANNEL B)
AD9284
RBIAS AGND AVDD DRVDD DRGND
09085-001
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011 Analog Devices, Inc. All rights reserved.
AD9284 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 SPI Timing Specifications ........................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Equivalent Circuits ......................................................................... 12 Theory of Operation ...................................................................... 13 ADC Architecture ...................................................................... 13 Analog Input Considerations.................................................... 13 Voltage Reference ....................................................................... 13 RBIAS........................................................................................... 13 Clock Input Considerations...................................................... 14 Digital Outputs ........................................................................... 14 Built-In Self-Test (BIST) and Output Test .................................. 15 Built-In Self-Test (BIST)............................................................ 15 Output Test Modes..................................................................... 15 Serial Port Interface (SPI).............................................................. 16 Configuration Using the SPI..................................................... 16 Hardware Interface..................................................................... 17 Configuration Without the SPI ................................................ 17 SPI Accessible Features.............................................................. 17 Memory Map .................................................................................. 18 Reading the Memory Map Register Table............................... 18 Memory Map Register Table..................................................... 19 Memory Map Register Descriptions........................................ 21 Applications Information .............................................................. 22 Design Guidelines ...................................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
1/11--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD9284 SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, unless otherwise noted. Table 1.
Parameter 1 RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTICS Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUT Input Span Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) Full Power Bandwidth VOLTAGE REFERENCE Internal Reference Input Resistance POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD IDRVDD POWER CONSUMPTION Sine Wave Input 2 Power-Down Power
1
Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Min 8
Typ
Max
Unit Bits LSB LSB % FS % FS % FS % FS ppm/C ppm/C V p-p V k fF MHz
0 0 0 0
0.2 0.1 Guaranteed 0.4 2.5 0.5 0.1 2 20 1.2 1.4 16 250 700
0.4 0.3 2.1 2.8 2.6 0.7
0.97
0.98 3
0.99
V k
Full Full Full Full Full Full
1.7 1.7
1.8 1.8 124 51 314 0.3
1.9 1.9 128 54 330 1.7
V V mA mA mW mW
2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. Measured with a low frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Rev. 0 | Page 3 of 24
AD9284
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, maximum sample rate, VIN = -1.0 dBFS differential input, unless otherwise noted. Table 2.
Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz WORST OTHER HARMONIC OR SPUR fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz CROSSTALK Temperature 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C 25C 25C Full 25C Full Min Typ 49.3 49.3 49.3 49.3 49.2 49.2 49.2 49.2 7.9 7.9 7.9 7.9 -70 -70 -70 -65 70 70 69 65 -71 -71 -70 -67 -80 Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
48.7
48.5
7.8
-61
61
-64
Rev. 0 | Page 4 of 24
AD9284
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted. Table 3.
Parameter 1 CLOCK INPUTS (CLK+, CLK-) Logic Compliance Internal Common-Mode Bias Differential Input Voltage 2 Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance (Differential) Input Capacitance LOGIC INPUTS CSB High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance SCLK, SDIO/PWDN, OE High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS (D7+, D7- to D0+, D0-), LVDS DRVDD = 1.8 V Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default)
1
Temperature
Min
Typ LVDS/PECL 1.2
Max
Unit
Full Full Full Full Full Full Full 25C 25C
0.2 AVDD - 0.3 1.2 0 -10 -10 20 4
6 AVDD + 1.6 3.6 0.8 +10 +10
V V p-p V V V A A k pF
Full Full Full Full 25C 25C Full Full Full Full 25C 25C
1.2 0 -5 -80
-0.4 -63 30 2
DRVDD + 0.3 0.8 +5 -50
V V A A k pF V V A A k pF
1.2 0 50 -5
57 -0.4 30 2
DRVDD + 0.3 0.8 70 +5
Full Full
290 1.15
345 1.25 Offset binary
400 1.35
mV V
2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. Specified for LVDS and LVPECL only.
Rev. 0 | Page 5 of 24
AD9284
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, -1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4.
Parameter CLOCK INPUT PARAMETERS Input Clock Rate CLK Period (tCLK) CLK Pulse Width High (tCH) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO to Data Skew (tSKEW) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time1 OUT-OF-RANGE RECOVERY TIME
1
Temperature Full Full Full
Min 30 7.4
Typ
Max 250
Unit MHz ns ns ns ns ps Cycles ns ps rms s Cycles
3.7 3.7 3.7 -60 10.5 1.0 0.1 500 2
Full Full Full Full Full Full Full
-280
+100
Wake-up time is dependent on the value of the decoupling capacitors.
SPI TIMING SPECIFICATIONS
Table 5.
Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Min 2 2 40 2 2 10 10 10 10 Typ Max Unit ns ns ns ns ns ns ns ns ns
Timing Diagram
M-1 M VINA M+3 M+1 N N+1 M+2 N+3 N+2 N+4 M+4 M+5
tA
N-1 VINB
N+5
tCH
CLK+ CLK- DCO+, DCO- CH A, CH B
tCLK
tDCO tSKEW
DATA CH A, CH B
N - 11 M - 10 N - 10
M-9
N-9
M-8
N-8
M-7
N-7
tPD
Figure 2. Output Data Timing
Rev. 0 | Page 6 of 24
09085-002
AD9284 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Electrical AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0- through D7+/D7- to DRGND DCO+, DCO- to DRGND CLK+, CLK- to AGND VINA, VINB to AGND SDIO/PWDN to DRGND CSB to AGND SCLK to AGND Environmental Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +2.0 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -65C to +125C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance
Package Type 48-Lead LFCSP (CP-48-12) JA 30.4 JC 2.9 Unit C/W
ESD CAUTION
Rev. 0 | Page 7 of 24
AD9284 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37 AVDD VIN-B VIN+B AVDD AVDD VREF AVDD VCM AVDD VIN+A VIN-A AVDD
AVDD AVDD
1 2
PIN 1 INDICATOR
DNC 3 DNC 4 RBIAS 5 DNC 6 DRGND 7 DRVDD 8 D0- (LSB) 9 D0+ (LSB) 10 D1- 11 D1+ 12
AD9284
TOP VIEW (Not to Scale)
36 35 34 33 32 31 30 29 28 27 26 25
AVDD AVDD CLK+ CLK- CSB SDIO/PWDN SCLK OE DRGND DRVDD D7+ (MSB) D7- (MSB)
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. ADC Power Pins 1, 2, 35, 36, 37, 40, 42, 44, 45, 48 8, 27 7, 28 0 Mnemonic AVDD DRVDD DRGND AGND Type Supply Supply Ground Ground Description Analog Power Supply (1.8 V Nominal). Digital Output Driver Supply (1.8 V Nominal). Digital Output Ground. Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. This is the only ground connection, and it must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (-) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (-) for Channel B. Voltage Reference Input/Output. External Reference Bias Resistor. Connect 10 k from RBIAS to AGND. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input--True. ADC Clock Input--Complement. Digital Enable (Active Low) to Tristate Output Data Pins. Channel A/Channel B LVDS Output Data 7--True. Channel A/Channel B LVDS Output Data 7--Complement. Channel A/Channel B LVDS Output Data 6--True. Channel A/Channel B LVDS Output Data 6--Complement. Channel A/Channel B LVDS Output Data 5--True. Channel A/Channel B LVDS Output Data 5--Complement. Channel A/Channel B LVDS Output Data 4--True. Channel A/Channel B LVDS Output Data 4--Complement.
Rev. 0 | Page 8 of 24
ADC Analog Pins 39 38 46 47 43 5 41 34 33 Digital Input 29 Digital Outputs 26 25 24 23 22 21 20 19
VIN+A VIN-A VIN+B VIN-B VREF RBIAS VCM CLK+ CLK- OE D7+ (MSB) D7- (MSB) D6+ D6- D5+ D5- D4+ D4-
Input Input Input Input Input/output Input/output Output Input Input Input Output Output Output Output Output Output Output Output
09085-003
NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
D2- D2+ D3- D3+ DCO- DCO+ D4- D4+ D5- D5+ D6- D6+
13 14 15 16 17 18 19 20 21 22 23 24
AD9284
Pin No. 16 15 14 13 12 11 10 9 18 17 SPI Control Pins 30 31 32 Do Not Connect 3, 4, 6 Mnemonic D3+ D3- D2+ D2- D1+ D1- D0+ (LSB) D0- (LSB) DCO+ DCO- SCLK SDIO/PWDN CSB DNC Type Output Output Output Output Output Output Output Output Output Output Input Input/output Input N/A Description Channel A/Channel B LVDS Output Data 3--True. Channel A/Channel B LVDS Output Data 3--Complement. Channel A/Channel B LVDS Output Data 2--True. Channel A/Channel B LVDS Output Data 2--Complement. Channel A/Channel B LVDS Output Data 1--True. Channel A/Channel B LVDS Output Data 1--Complement. Channel A/Channel B LVDS Output Data 0--True. Channel A/Channel B LVDS Output Data 0--Complement. Channel A/Channel B LVDS Data Clock Output--True. Channel A/Channel B LVDS Data Clock Output--Complement. SPI Serial Clock. SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). SPI Chip Select (Active Low). Do Not Connect. Do not connect to this pin.
Rev. 0 | Page 9 of 24
AD9284 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.2 V p-p differential input, VIN = -1.0 dBFS, 64k sample, TA = 25C, unless otherwise noted.
0 250MSPS 4.3MHz @ -1dBFS SNR = 48.3dB (49.3dBFS) ENOB = 7.7 SFDR = 70.3dBc
0
-20
-20
250MSPS 96.6MHz @ -1dBFS SNR = 48.3dB (49.3dBFS) ENOB = 7.7 SFDR = 70.0dBc
AMPLITUDE (dBFS)
-40 SECOND HARMONIC -60 THIRD HARMONIC -80
AMPLITUDE (dBFS)
-40 SECOND HARMONIC -60 THIRD HARMONIC
-80
-100
-100
09085-107
0
25
50
75
100
125
0
25
50
75
100
125
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Single-Tone FFT with fIN = 4.3 MHz
0
0
Figure 7. Single-Tone FFT with fIN = 96.6 MHz
250MSPS 330.3MHz @ -1dBFS SNR = 48.2dB (49.2dBFS) -20 ENOB = 7.6 SFDR = 60.9dBc
AMPLITUDE (dBFS)
-20
250MSPS 29.2MHz @ -7dBFS 32.2MHz @ -7dBFS SFDR = 69.6dBc (76.6dBFS)
AMPLITUDE (dBFS)
-40 THIRD HARMONIC SECOND HARMONIC
-40
-60
-60
-80
-80
-100
-100
0 25 50 75 100 125
09085-111
-120
09085-108
-120 0 25 50 75 100 125 FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Single-Tone FFT with fIN = 220.3 MHz
80 70 SFDR (dBFS) 60 50 40 30 20 10 0 -45 SNR (dBc)
Figure 8. Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz
80 70 60 IMD3 (dBFS)
SFDR/IMD3 (dB)
SFDR/SNR (dB)
SNR (dBFS) REFERENCE LINE
SFDR (dBFS) 50 40 IMD3 (dBc) 30 SFDR (dBc) 20 10 0 -45
SFDR (dBc)
09085-109
-40
-35
-30
-25
-20
-15
-10
-5
0
-40
-35
-30
-25
-20
-15
-10
-5
0
AIN POWER (dBFS)
AIN POWER (dBFS)
Figure 6. SFDR/SNR vs. Input Amplitude (AIN) with fIN = 2.2 MHz
Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz
Rev. 0 | Page 10 of 24
09085-112
09085-110
-120
-120
AD9284
75 50.0
0.15
70
49.8
0.10
SFDR (dBc)
65
SNRFS: SIDE A
49.6
INL ERROR (LSB)
SNRFS (dBFS)
SFDR: SIDE A
SFDR: SIDE B
0.05
0
60 SNRFS: SIDE B 55
49.4
-0.05
49.2
-0.10
50 50 49.0 250
ENCODE (MSPS)
0
32
64
96
128
160
192
224
256
OUTPUT CODE
Figure 10. SNRFS/SFDR vs Encode with fIN = 2.4 MHz
0.15
Figure 12. INL Error with fIN = 4.3 MHz
0.10
DNL ERROR (LSB)
0.05
0
-0.05
-0.10
0
32
64
96
128
160
192
224
256
OUTPUT CODE
Figure 11. DNL Error with fIN = 4.3 MHz
Rev. 0 | Page 11 of 24
09085-115
-0.15
09085-117
75
100
125
150
175
200
225
09085-113
-0.15
AD9284 EQUIVALENT CIRCUITS
AVDD AVDD 1.2V 10k 10k AVDD
DRVDD DRVDD
CLK-
CLK+
SCLK, OE, AUXCLKEN
09085-019
350 30k
09085-022
Figure 13. Clock Inputs
Figure 16. SCLK, OE
AVDD BUF 8k AVDD BUF 8k
09085-020
VIN+
AVDD
DRVDD 350
VCML ~1.4V
30k SDIO
09085-023
09085-024
VIN-
BUF
CTRL
Figure 14. Analog Inputs (VCML = ~1.4 V)
Figure 17. SDIO
DRVDD
DRVDD DRVDD 30k DRVDD
V+ D7- TO D0- V-
09085-021
V- D7+ TO D0+ V+
CSB
350
Figure 15. CSB
Figure 18. LVDS Output Driver
Rev. 0 | Page 12 of 24
AD9284 THEORY OF OPERATION
The AD9284 is a pipeline-type converter. The input buffers are differential, and both sets of inputs are internally biased. This allows the use of ac or dc input modes. A sample-and-hold amplifier is incorporated into the first stage of the multistage pipeline converter core. The output staging block aligns the data, carries out error correction for the pipeline stages, and feeds that data to the output buffers. The two ADC channels are sampled simultaneously through a single encoding clock. All user-selected options are programmed through dedicated digital input pins or a serial port interface (SPI).
Differential Input Configurations
Optimum performance is achieved when driving the AD9284 in a differential input configuration. For baseband applications, the ADA4937-1 differential driver provides excellent performance and a flexible interface to the ADC (see Figure 19). The output common-mode voltage of the AD9284 is easily set to 1.4 V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
200 1.2V p-p 61.9 200 33
ADC ARCHITECTURE
Each channel of the AD9284 consists of a differential input buffer followed by a sample-and-hold amplifier (SHA). The SHA is followed by a pipeline switched-capacitor ADC. The quantized outputs from each stage are combined into a final 8-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, whereas the remaining stages operate on preceding samples. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended mode. The output staging block aligns the data, carries out error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers enter a high impedance state.
0.1F
- ADA4937-1
4.7pF
AD9284
+ VIN
09085-025
227.4
+
200
33
-
VCM
Figure 19. Differential Input Configuration Using the ADA4937-1
The AD9284 can also be driven passively with a differential transformer-coupled input (see Figure 20). To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer.
33 1.2V p-p 49.9 4.7pF 33 VCM
09085-026
AD9284
+ - VIN
0.1F
Figure 20. Differential Transformer-Coupled Configuration
ANALOG INPUT CONSIDERATIONS
The analog inputs of the AD9284 are differentially buffered. For best dynamic performance, the source impedances driving VIN+A, VIN+B, VIN-A, and VIN-B should be matched such that common-mode settling errors are symmetrical. The analog inputs are optimized to provide superior wideband performance and must be driven differentially. SNR and SINAD performance degrades significantly if the analog inputs are driven with a singleended signal. A wideband transformer, such as Mini-Circuits(R) ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.4 V.
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion.
VOLTAGE REFERENCE
An internal differential voltage reference creates positive and negative reference voltages that define the 1.2 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of SPI control. It can also be driven externally with an off-chip stable reference. See the Memory Map Register Descriptions section for more details.
RBIAS
The AD9284 requires the user to place a 10 k resistor between the RBIAS pin and ground. This resistor, which is used to set the master current reference of the ADC core, should have a 1% tolerance.
Rev. 0 | Page 13 of 24
AD9284
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9284 sample clock inputs, CLK+ and CLK- with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 23. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance.
CLOCK INPUT 0.1F 0.1F CLK+
Clock Input Options
The AD9284 has a very flexible clock input structure. The clock input can be an LVDS, LVPECL, or sine wave signal. Each configuration that is described in this section applies to CLK+ and CLK-. Figure 21 and Figure 22 show the two preferred methods for clocking the AD9284. A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer or an RF balun. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9284 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9284, while preserving the fast rise and fall times of the signal that are critical to low jitter performance.
Mini-Circuits(R) ADT1-1WT, 1:1 Z CLOCK INPUT 0.1F 50 100 XFMR 0.1F CLK+
AD951x
CLOCK INPUT 50k 0.1F 50k PECL DRIVER 240
100 0.1F 240
ADC
CLK-
09085-029
Figure 23. Differential PECL Sample Clock
A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 24. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance.
CLOCK INPUT 0.1F 0.1F CLK+
AD951x
CLOCK INPUT 50k 0.1F 50k LVDS DRIVER
100 0.1F
ADC
CLK-
09085-030
ADC
CLK-
09085-027
Figure 24. Differential LVDS Sample Clock
0.1F
0.1F
SCHOTTKY DIODES: HSM2822
DIGITAL OUTPUTS
Digital Output Enable Function (OE)
The AD9284 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OE pin. When OE is set to logic level high, the output drivers for both data buses are placed into a high impedance state.
Figure 21. Transformer-Coupled Differential Clock
CLOCK INPUT 50
1nF CLK+ 0.1F 1nF 0.1F SCHOTTKY DIODES: HSM2822
ADC
CLK-
09085-028
Figure 22. Balun-Coupled Differential Clock
Rev. 0 | Page 14 of 24
AD9284 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9284 includes a built-in self-test feature that is designed to enable verification of the integrity of each channel, as well as facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9284 is included. Various output test options are also provided to place predictable values on the outputs of the AD9284. Writing a value of 0x05 to Register 0x0E runs the BIST. This enables Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (BIST init) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x0E is automatically cleared. The PN sequence can be continued from its last value by writing a 0 to Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user must rely on verifying the output data.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected AD9284 signal path. Perform the BIST test after a reset to ensure that the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. When the test is completed, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 of Register 0x0E, signifying that the test passed. If the BIST test fails, Bit 0 of Register 0x0E is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs.
OUTPUT TEST MODES
The output test options are described in Table 12 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks, and the test pattern is run through the output formatting block. Some test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Rev. 0 | Page 15 of 24
AD9284 SERIAL PORT INTERFACE (SPI)
The AD9284 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 25. Other modes involving CSB are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. CSB can stall high between bytes to allow for additional external timing. When the CSB pin is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. During the instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits, as shown in Figure 25. All data is composed of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, the serial data input/output (SDIO) pin changes direction, from an input to an output, at the appropriate point in the serial frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: SCLK, SDIO, and CSB (see Table 9). SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. CSB (chip select bar) is an active low control that enables or disables the read and write cycles. Table 9. Serial Port Interface Pins
Pin SCLK SDIO Function Serial clock. A serial shift clock input that is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles.
CSB
tDS tS
CSB
tHIGH tDH tLOW
tCLK
tH
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON'T CARE
Figure 25. Serial Port Interface Timing Diagram
Rev. 0 | Page 16 of 24
09085-004
AD9284
HARDWARE INTERFACE
The pins described in Table 9 constitute the physical interface between the programming device of the user and the serial port of the AD9284. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9284 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SDIO/PWDN serves a dual function when the SPI interface is not being used. When the pin is strapped to AVDD or ground during device power-on, it is associated with a specific function. The mode selection table (see Table 10) describes the strappable functions that are supported on the AD9284. Table 10. Mode Selection
Pin SDIO/PWDN OE External Voltage AVDD (default) AGND AVDD AGND (default) Configuration Chip in full power-down Normal operation Outputs in high impedance Outputs enabled
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers, the SDIO/PWDN pin serves as a standalone, CMOS-compatible control pin. When the device is powered up, it is assumed that the user intends to use the SDIO, SCLK, and CSB pins as static control lines for the output enable and power-down feature control. In this mode, connecting the CSB chip select to AVDD disables the serial port interface.
SPI ACCESSIBLE FEATURES
Table 11 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9284 part-specific features are described in detail in Table 12. Table 11. Features Accessible Using the SPI
Feature Mode Clock Offset Test I/O Output Mode Output Phase Output Delay Voltage Reference Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the voltage reference
Rev. 0 | Page 17 of 24
AD9284 MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table (see Table 12) has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02), the device index and transfer registers (Address 0x05 and Address 0xFF), and the program registers (Address 0x08 to Address 0x25). Table 12 documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0xFF.
Logic Levels
An explanation of logic level terminology follows: * * "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." "Bit is cleared" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit."
Transfer Register Map
Address 0x08 to Address 0x38 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. Setting the transfer bit allows these registers to be updated internally and simultaneously. The internal update takes place when the transfer bit is set, and then the bit autoclears.
Open Locations
All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open. If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written.
Channel-Specific Registers
Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in the memory map register table as local. These local registers and bits can be accessed by setting the appropriate Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during a SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.
Default Values
After the AD9284 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 12).
Rev. 0 | Page 18 of 24
AD9284
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 12 are not currently supported for this device. Table 12. Memory Map Registers
Addr Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 0 SPI port configuration Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments Nibbles are mirrored so that LSB-first or MSB-first mode registers correctly, regardless of shift mode Unique chip ID used to differentiate devices; read only Unique speed grade ID is used to differentiate devices; read only Bits are set to determine which on-chip device receives the next write command; default is all devices on the chip Synchronous transfer of data from the master shift register to the slave Determines various generic modes of chip operation
0x01
Chip ID (global)
8-bit chip ID
0x0A
0x02
Chip grade (global)
Open
Speed grade ID 000 = 250 MSPS
Open
0x00
Device Index and Transfer Registers 0x05 Device Index A
Open
ADC B default
ADC A default
0xFF
0xFF
Transfer
Open
Transfer
0xFF
Program Registers (May or may not be indexed by device index) 0x08 Open Modes (global)
Internal power-down mode 00: chip run 01: full power-down 10: reserved 11: reserved Clock Duty cycle boost stabilizer Output test mode 000: off 001: midscale short 010: +FS short 011: -FS short 100: checkerboard output 101: PN23 sequence 110: PN9 sequence 111: one-/zero-word toggle BIST init Open BIST enable
0x00
0x09 0x0D
Clock (global) Test mode (local)
Open Open Reset PN23 gen Reset PN9 gen Open
0x01 0x00 When test mode is set, test data is placed on the output pins in place of normal data
0x0E
BIST (local)
Open
0x00
BIST mode config
Rev. 0 | Page 19 of 24
AD9284
Addr (Hex) 0x0F Register Name ADC input (global/local) Bit 7 (MSB) Bit 6 Bit 5 Open Bit 4 Bit 3 Bit 1 Commonmode input enable (global) Offset adjust (twos complement format) 0111: +7 0110: +6 ... 0001: +1 0000: 0 1111: -1 ... 1001: -7 1000: -8 Open Data format select Output invert 00: offset binary 01: twos complement 10: Gray code 11: reserved Open Bit 2 Analog disconnect (local) Bit 0 (LSB) Open Default Value (Hex) 0x00 Default Notes/ Comments
0x10
Offset (local)
Open
0x00
Device offset trim
0x14
Output mode (local)
Open
Output enable
0x00
Configures the outputs and the format of the data
0x16
0x18
0x24
Output phase (global) Voltage reference (global) MISR LSB (local)
DCO invert
0x00
Open
Voltage reference and input full-scale adjustment (see Table 13)
0x00
Selects/ adjusts VREF MISR least significant byte; read only MISR most significant byte; read only
LSBs of multiple input shift register (MISR)
0x00
0x25
MISR MSB (local)
MSBs of multiple input shift register (MISR)
0x00
Rev. 0 | Page 20 of 24
AD9284
MEMORY MAP REGISTER DESCRIPTIONS
For more information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Table 13. VREF and Input Full Scale (Register 0x18)
Value 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 VREF (V) 0.844 0.857 0.87 0.883 0.896 0.909 0.922 0.935 0.948 0.961 0.974 0.987 1 1.013 1.026 1.039 1.052 1.065 1.078 1.091 1.104 1.117 1.13 1.143 1.156 1.169 1.182 1.195 1.208 1.221 1.234 External Full Scale (V) 1.013 1.028 1.044 1.060 1.075 1.091 1.106 1.122 1.138 1.153 1.169 1.184 1.200 1.216 1.231 1.247 1.262 1.278 1.294 1.309 1.325 1.340 1.356 1.372 1.387 1.403 1.418 1.434 1.450 1.465 1.481 External x 1.2
Voltage Reference (Register 0x18) Bits[7:5]--Reserved Bits[4:0]--Voltage Reference
Bits[4:0] scale the internally generated voltage reference and, consequently, the full scale of the analog input. Within this register, the reference driver can be configured to be more easily driven externally by reducing the capacitive loading. The relationship between the VREF voltage and the input full scale is described by Equation 1. See Table 13 for a complete list of register settings. Input_Full_Scale = VREF x 1.2 (1)
Rev. 0 | Page 21 of 24
AD9284 APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9284 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
Power and Ground Recommendations
When connecting power to the AD9284, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and DRVDD supply must be used, the AVDD and DRVDD domains must be isolated with a ferrite bead or filter choke and separate decoupling capacitors. Several different decoupling capacitors can be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the printed circuit board (PCB) level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9284. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved.
VCM
The VCM pin should be decoupled to ground with a 0.1 F capacitor.
RBIAS
The AD9284 requires that a 10 k resistor be placed between the RBIAS pin and ground. This resistor, which sets the master current reference of the ADC core, should have at least a 1% tolerance.
Reference Decoupling
Decouple the VREF pin externally to ground with a low ESR, 1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic capacitor.
Exposed Paddle Thermal Heat Sink Recommendations
The exposed paddle (Pin 0) is the only ground connection for the AD9284; therefore, it must be connected to analog ground (AGND) on the customer PCB. To achieve the best electrical and thermal performance, mate an exposed (no solder mask), continuous copper plane on the PCB to the AD9284 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9284 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Rev. 0 | Page 22 of 24
AD9284 OUTLINE DIMENSIONS
7.10 7.00 SQ 6.90 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
6.85 6.75 SQ 6.65
0.50 REF
(BOTTOM VIEW)
EXPOSED PAD
*4.70 4.60 SQ 4.50
25 24
13
12
TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12 MAX 0.80 MAX 0.65 TYP
0.50 0.40 0.30
0.25 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
04-22-2010-A
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 26. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-12) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD9284BCPZ-250 AD9284BCPZRL7-250 AD9284-250EBZ
1
Temperature Range -40C to +85C -40C to +85C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-48-12 CP-48-12
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
AD9284 NOTES
(c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09085-0-1/11(0)
Rev. 0 | Page 24 of 24

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